Forum Discussion
Occasional ContributorLow Latency 100G Ethernet Intel FPGA IP Hardware Design Example
Hi everyone,
I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described in alt_e100s10.v twice inside a top level module. The only doubt is given by the avalon jtag master bridge. Can i instantiate two of them, one for each instance? And if not, can i use the Ethernet Link Inspector for the two different instances with only 1 avalon jtag master bridge?
If i was not clear enough, please ask me questions.
Thank you.
12 Replies
SengKok_L_IntelRegular Contributor
Hi,
Yes, you can use Avalon Jtag master bridge for more than 1 Ethernet IP, what you need to do is to ensure it has a difference base address.
Regards -SK
AGaru1Thanks for your answer.
If i correctly understood i can use two Avalon Jtag master bridges, one for each Ethernet IP, as long as they have a different base address.
- SengKok_L_Intel
You can use ONE Jtag Master connects to two Ethernet IP with a difference base addresses.
- AGaru1
Thank you, i get it now. Can you at last confirm if this architecture is correct?
- AGaru1
- SengKok_L_Intel
Yes, it looks fine.
Regards -SK
- AGaru1
Can the addressing be managed by the system console somehow?
Do i need to create a demux to route the data to the right IP or there is any tool in quartus that makes it?
- AGaru1
I've noticed this part on the ethernet_link_inspector guide:
3. In the Ethernet Link Inspector - Link Monitor tab, follow these steps to set the
correct JTAG to Avalon Master path:
a. Load the Programming File (*.sof) in System Console by clicking File ➤
Load Design for the detailed JTAG to Avalon Master path.
b. Select List JTAG Masters to see all available JTAG to Avalon Master paths.
c. Select a JTAG to Avalon Master path number from the drop-down box and click
Set JTAG Master.
Note: Each JTAG to Avalon Master path lists two TYPE_NAME (marked by the
blue box in the figure below). The instance name of the JTAG to Avalon
Master path is displayed in one of these TYPE_NAME along with the text
FULL_HPATH (marked by the orange box in the figure below). Select the
JTAG to Avalon Master path number that has the instance name of the
JTAG to Avalon Master path connected to the Ethernet IP.
Seems like they are using multiple jtag masters and then choosing the connected to the IP of interest.
- SengKok_L_Intel
Yes, if using more than one Jtag master, there will have multiple IDs, and you need to select the right one for each instance. To assign the base address, one of the methods is to use avmm master bridge from platform designer (One Jtag Master connect to two AVMM master bridge).
Regards -SK
- SengKok_L_Intel
Since there are no recent activities, I’ll set this case to close-pending. If you’re still in need of assistance, please reopen this case within the next 20 days.
