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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

Hi everyone, I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Yes, if using more than one Jtag master, there will have multiple IDs, and you need to select the right one for each instance. To assign the base address, one of the methods is to use avmm master bridge from platform designer (One Jtag Master connect to two AVMM master bridge).

Regards -SK