Forum Discussion
AGaru1
Occasional Contributor
Occasional ContributorLow Latency 100G Ethernet Intel FPGA IP Hardware Design Example
Hi everyone, I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described ...
SengKok_L_Intel
Regular Contributor
Regular ContributorYou can use ONE Jtag Master connects to two Ethernet IP with a difference base addresses.
