Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

Hi,

i temporarely stopped working on transceivers. Now i'm back on it and i'm trying to figure out the pinout. I downloaded the 1SM21C document by Intel.

I don't understand the relation between the pins and the transceivers. For example, the board i'm using is a BittWare 520N-MX with an Intel Stratix-10 FPGA connected to four QSFP28 ports.

I need to use two of those QSFP28 ports. In particular i need to use the Ethernet 100Gb Hard IP which seems to be usable via port 2 and 3 on the board. So i'm looking forward to the pinout of the port 2 and 3.

The board document says that:

QSFP0_RX[0]p -> pin BB45

QSFP0_RX[0]n -> pin BB44

QSFP0_TX[0]p -> pin BD49

QSFP0_TX[0]n -> pin BD48

and then it says that the rest of the pin mappings follow numerically.

Then i took a look at the Intel document 1SM21C.

I'm a bit confused because in the verilog code RX and TX wires are buses [3:0] so each of them is made of 4 wires.

I don't understand what pin corresponds to each of those wires and also how do i differentiate each QSFP(n) from each other.

For example, i want to use QSFP2 and QSFP3 and i know that each rx and tx wires are composed of 4 wires each. How should i look at the Intel document?

Sorry i'm new to it ...