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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

Hi everyone, I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described ...
AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi i have another question. I made a wrapper with 2 instances of the IP. It gets synthetized and implemented correctly but it doesn't pass the timing analysis (there is an epic slack, like -90). I don't understand why, i'm looking the paths and it seems like it's something related to the pll that generates the clk100. Have you got any advice please?