Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

I've noticed this part on the ethernet_link_inspector guide:

3. In the Ethernet Link Inspector - Link Monitor tab, follow these steps to set the

correct JTAG to Avalon Master path:

a. Load the Programming File (*.sof) in System Console by clicking File ➤

Load Design for the detailed JTAG to Avalon Master path.

b. Select List JTAG Masters to see all available JTAG to Avalon Master paths.

c. Select a JTAG to Avalon Master path number from the drop-down box and click

Set JTAG Master.

Note: Each JTAG to Avalon Master path lists two TYPE_NAME (marked by the

blue box in the figure below). The instance name of the JTAG to Avalon

Master path is displayed in one of these TYPE_NAME along with the text

FULL_HPATH (marked by the orange box in the figure below). Select the

JTAG to Avalon Master path number that has the instance name of the

JTAG to Avalon Master path connected to the Ethernet IP.

Seems like they are using multiple jtag masters and then choosing the connected to the IP of interest.