Forum Discussion
AGaru1
Occasional Contributor
Occasional ContributorLow Latency 100G Ethernet Intel FPGA IP Hardware Design Example
Hi everyone, I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described ...
AGaru1Occasional Contributor
Occasional ContributorCan the addressing be managed by the system console somehow?
Do i need to create a demux to route the data to the right IP or there is any tool in quartus that makes it?
