Occasional ContributorJESD204B rx_islockedtodata signal issue
Hello,
My device version is stratix10 1SX110HN2F43I2VG. I use FPGA to receive JESD204B data from ADC chip. When I power up the PCB, both the FPGA and ADC do not have device clock input, or the input is at a lower erroneous frequency.Then I configure the clock chip through SPI so that both the ADC and FPGA receive the correct device clock. However, the ADC still does not output JESD204B data. Then, I configure the ADC through SPI to output JESD204B data. I found that the rx_islockedtodata signal is 0. I tried disconnecting the xcvr_reset_control IP core, manually resetting rx_analogreset and rx_digitalreset, but still could not make rx_islockedtodata high. After reconnecting the xcvr_reset_control IP core and reloading the sof file, rx_islockedtodata successfully becomes 0xF. This means that even though the FPGA has received the 204B data rx_islockedtodata remains at 0. After reloading the sof file again, rx_islockedtodata becomes 0xF. How can I bring the rx_islockedtodata signal high without reloading the sof file? Or what variables during the process of reloading the sof file cause the rx_islockedtodata signal to go high? Does the FPGA only program sof file when ensuring JESD204B data input?
thanks
Hi,
Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).
Can you please share the reason for configuring LMK04832 via SPI for every power cycle?
Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.
If not, other solutions:
- Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
- You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.
Regards,
HarshX
