Forum Discussion
Occasional ContributorJESD204B rx_islockedtodata signal issue
Hi,
Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).
Can you please share the reason for configuring LMK04832 via SPI for every power cycle?
Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.
If not, other solutions:
- Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
- You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.
Regards,
HarshX
Occasional ContributorHi,
I hope you do have main reset signal in your design, use that (Here I'm guessing that resetting only the JESD204B is not working).
About how you can change the values/variables once the FPGA is programmed ->SYSTEM DEBUGGING TOOLS -> you can use ISSP (In-System Sources and Probes), you have to implement this in your design beforehand. By using Intel System Console GUI you can give command to make changes in your design (enabling reset, changing values, etc) on run.
ISSP: 1.3.1. In-System Sources and Probes (intel.com)
System Console: 7.1. Introduction to System Console (intel.com)
Kindly also answer queries in previous comments.
I hope this info is useful.
Regards,
HarshX
Occasional ContributorI attempted to manually control rx_analogreset and rx_digitalreset of the jesd204b IP core through ISSP, affter LMK04832 is configured , but it didn't work. It seems that configuring LMK04832 before FPGA is the only solution.
