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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

JESD204B rx_islockedtodata signal issue

Hello, My device version is stratix10 1SX110HN2F43I2VG. I use FPGA to receive JESD204B data from ADC chip. When I power up the PCB, both the FPGA and ADC do not have device clock input, or the i...
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  • Harshx's avatar
    Harshx
    1 year ago

    Hi,

    Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).

    Can you please share the reason for configuring LMK04832 via SPI for every power cycle?

    Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.


    If not, other solutions:

    1. Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
    2. You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.


    Regards,

    HarshX


Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

Thanks for contacting Intel.

I'm assigned to support request.

I'll investigate on this case.

Can you please share the following details:

  1. Quartus version you are using.
  2. Which Clock Chip you are using (as mentioned in your block diagram) -> This is just to figure out is there any default clock setting? if you program the clock and power cycle the board is it able to retain the settings?


Thanks for your patience.

Best regards,

HarshX


  • allen18's avatar
    allen18
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi

    I am using quartus Pro 22.3 , clock chip is LMK04832 , according to my latest findings, before configuring the FPGA, the transceiver must has a stable reference clock. before loading the .sof file for the first time, the clock chip was not configured, leaving the transceiver without a reference clock. After loading the .sof file, the FPGA automatically configured the clock chip, then the clock chip consistently provided stable output. Therefore, by the time I load the .sof file for the second time, the transceiver already had a stable reference clock, and rx_islockedtodata change to high.I'm not entirely sure if this is the root cause of the issue

    .