Forum Discussion
Occasional ContributorJESD204B rx_islockedtodata signal issue
Hi,
Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).
Can you please share the reason for configuring LMK04832 via SPI for every power cycle?
Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.
If not, other solutions:
- Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
- You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.
Regards,
HarshX
Occasional ContributorThank you. We didn't notice this when designing the clock scheme for the project initially. It should be more reasonable to configure the clock chip in another way. The changes will be implemented in the next version of the PCB.
Occasional ContributorHi allen18,
right now i am facing the same issue, i am using different clock IC ,May I know How you resolved this issue. It would very helpful.
Thanks In advance.
- allen18
You need to provide stable reference clocks of jesd204b ip core before the start of FPGA configuration, I am currently using a microcontroller to configure the clock chip. After the configuration is complete, load the sof file to the FPGA, the jesd204b IP core can work properly.
- allen18
Another possibility is that your ADC does not output data, and only after receiving 8b10b code data and CDR clock is locking, will the rx_islockedtodata signal goes to 1.
