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allen18
Occasional Contributor
Occasional ContributorJESD204B rx_islockedtodata signal issue
Hello, My device version is stratix10 1SX110HN2F43I2VG. I use FPGA to receive JESD204B data from ADC chip. When I power up the PCB, both the FPGA and ADC do not have device clock input, or the i...
Hi,
Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).
Can you please share the reason for configuring LMK04832 via SPI for every power cycle?
Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.
If not, other solutions:
- Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
- You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.
Regards,
HarshX
HarshxOccasional Contributor
Occasional ContributorHi,
Yes the root cause is same as you mentioned - no ref clock when FPGA is configured (First time).
Can you please share the reason for configuring LMK04832 via SPI for every power cycle?
Can you program the LMK04832 once and it'll retain the clock configuration? -> If yes Do it.
If not, other solutions:
- Program the FPGA via jic and rbf -> So that even after power cycle FPGA will have its configuration and you just need to give a reset command to FPGA and it'll work. Power up-> FPGA program the clk chip via SPI -> Reset command for FPGA.
- You can implement BMC (Board Management Controller) in your design. BMC will configure the LMK chip first and then bring up the FPGA.
Regards,
HarshX
allen18Occasional Contributor
Occasional ContributorHi,
Thank you for your response , how can I make a reset command for FPGA after LMK04832 configuration complete?
