New ContributorIssue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)
I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1).
In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory and an additional DDR4 external memory component. This setup by itself works fine.
The problem appears when I try to get HDMI output using the default IP cores. My design is similar to what I previously used on an older board (DE2-115). Whenever I connect the Pixel Buffer DMA controller’s AVMM host interface to the DDR4’s AXI slave, the CPU eventually hangs. It looks like an issue with the automatically generated AVMM → AXI translation.
To isolate the problem:
The Pixel Buffer → Video output system works in principle.
I tested the DMA controller with a custom “pixelbuffer_test” component, which simply returns the requested address on readdata. This setup worked.
The HDMI subsystem also works when driven by the Test Pattern Generator.
So the issue seems to arise specifically when the DMA master is connected to DDR4 via AVMM → AXI.
Question: Are there any known issues with AVMM ↔ AXI crossing in this configuration? Do you have ideas on how to solve this problem (other than writing my own AXI4 DMA controller or similar)?
I attached the Platform Designer system view, which shows both the working pixelbuffer_test connection and the intended DMA → DDR4 AXI connection. Note: the other DDR4 AXI4 subordinate connections go to Nios V’s data_manager and instruction_manager.
