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Wiede's avatar
Wiede
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3 months ago

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1). In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory a...
ShengN_altera's avatar
ShengN_altera
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3 months ago

Sure, understood that. Let me know once you got the update.


  • Wiede's avatar
    Wiede
    Icon for New Contributor rankNew Contributor
    2 months ago

    I finished trying your suggestions. Sadly, nothing seems to work. The interconnect still seems to freeze the system.