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Wiede's avatar
Wiede
Icon for New Contributor rankNew Contributor
11 months ago

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1). In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory a...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
11 months ago

Hi,


Understood that since there's no writeresponse valid signal so the “pending write transactions” cannot be set.


The DDR4 AXI is connected to multiple master which are NIOS V and DMA controller

Could you try using the Fixed Priority Arbitration check this https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/designate-a-slave-to-use-fixed-priority.html


May I know this connection you're refering to design example?


Thanks,

Regards,

Sheng