Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1). In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory a...