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Wiede's avatar
Wiede
Icon for New Contributor rankNew Contributor
3 months ago

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1). In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory a...
RichardT_altera's avatar
RichardT_altera
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2 months ago

Please be informed that starting October 1st, the FPGA Forum on community.intel.com will be placed in read-only mode.

You will still be able to view and access existing content, but new posts, comments, or edits will no longer be permitted during this transition period.

For urgent technical support, we kindly ask that you reach out through Intel Premier Support (IPS) via your DFAE (Altera authorised distributors) engagement.

We appreciate your patience as we prepare for the official launch of the new FPGA forum on October 14th, where posting capabilities will resume.

Thank you for your continued support and understanding.

Regards.

Richard Tan