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Wiede
New Contributor
New ContributorIssue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)
I’m working with the DE25-Standard board from Terasic, which has an Agilex5 FPGA (A5ED013BB32AE4SR1). In Quartus 25.1.1 Platform Designer, I’m using a Nios V/g CPU with the standard on-chip memory a...
ShengN_altera
Super Contributor
Super ContributorHi,
Also try some more interconnect settings https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/interconnect-parameters-59023.html:
Enable all pipeline stages: enable
Limit interconnect pipeline stages to: 4
Burst adapter implementation: Per-burst-type converter (faster, higher area)
Width adapter implementation: Optimized converter (faster, higher area)
Thanks,
Regards,
Sheng
