Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

Hi,

Also try some more interconnect settings https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/interconnect-parameters-59023.html:

Enable all pipeline stages: enable

Limit interconnect pipeline stages to: 4

Burst adapter implementation: Per-burst-type converter (faster, higher area)

Width adapter implementation: Optimized converter (faster, higher area)

Thanks,

Regards,

Sheng