issue in using EMIF interface for A10 SOC evaluation board

Hi Matt,

Thank you for joining this Intel Community.

May I know at which stage does the error seen? I have list down few possible causes that I suspect causing the issue. Kindly please take a look on it.

Please check on the following :

1. Check whether the mem* and rzq* signals exported to top level. The mem and rzq signal need to export to top level of the design because these signal is an interface signal between FPGA and memory module.
2. Is there any illegal connections on the DQ/DQS signals. The DQ/DQS signal should directly connect to I/O pin instead of any other logic, If you are connecting the DQ/DQS pin to the primitive, please remove it.
3. Based on past experience, if you have signal tap connected , it may cause you a problem . Please delete it from signal tap.

If everything is good, then perhaps, can you send me your design archive file and I can look in detail what is actually causing the error?

Let me know your feedback.

Thanks

Regards,

Aida

thanks Aida for your response.

I am using A10 Soc Evaluation board Rev C(production sample)A10AS066N3F40I2SG.

point 1: mem* and rzq* signals are exported to top level and oct_rzqin pin is connected to the ground in the schematic.

point 2: the DQ/DQS signals are directly connected to the pins.

point 3: i am not connecting signal tap

this error is coming during the Analysis & synthesis phase.

I want to add a few points, here in the example design tab in EMIF GUI i chose target development kit as "A10 SOC development kit with DDR HILO for FPGA(x72),

Since i didn't find the physical routing of dq pins to the connector for x72, and it has only 64 bit connection from FPGA to the connector,I modified the gui with the parameters in the example design which is mentioned below.

ref: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an829.pdf page: 8,

the board schematics is there in the following link

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html

Hi Matt,

Thanks for the reply.

Please allow me sometime to generate the example design and see if I can duplicate the issue from my side. Or it will be great if you can share your design archive with me and I can directly check it . 😊

Regards,

Aida

hello Aida,

thanks for your support

please find the design and please have a look.

Dear Matt,

Please accept my apology for the delay in response due to current workload.

When I compiled the design, I'm getting this message as below which is different from what you've encountered.

Error (17045): Input port I of I/O input buffer primitive top_hw|emif_1|emif_1|arch|arch_inst|bufs_inst|gen_mem_alert_n.inst[0].b|no_oct.ibuf is not connected. It must be driven by a top-level pin.

I double check on the mem_dqs and rzq connection and seems like the signals is OK.

I noticed that in your top level file (top.v), the mem_alert_n pin is not exported. After I exported this pin to the top level file, the design able to compile successfully. Attached is the QAR project for your reference.

Please try to run the design and let me know if this solved your problem.

Thanks

Regards,

Aida

Hello Aida,

Thank you so much for your support.

i think the emif ip which is there in the qsys and the one in example design are different. For example mem_alert_n pin is not there in the example design.

For this RevC A10 evaluation board i need to use the example design(design from rocketboards) instead of "A10 SOC development kit with DDR HILO for FPGA(x72)" which is there in qsys, as the physical routing is only for x64 and there is no provision to connect 8 ECC pins (x72)and I need to check the feasibility of connecting the extra pins like mem_alert_n in the evaluation board schematic.

Dear Matt,

Sure. I am sorry as I'm not familiar with rocketboards design. But, if there is anything I can help you, please let me know . 😊

Regards,

Aida