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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

issue in using EMIF interface for A10 SOC evaluation board

i have created design which contains the PCIe with dma and an emif interface in fpga. while trying to compile this design i am facing the following error. "Error(17044): Illegal connection on I/O i...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Matt,

Thank you for joining this Intel Community.

May I know at which stage does the error seen? I have list down few possible causes that I suspect causing the issue. Kindly please take a look on it.

Please check on the following :

  1. Check whether the mem* and rzq* signals exported to top level. The mem and rzq signal need to export to top level of the design because these signal is an interface signal between FPGA and memory module.
  2. Is there any illegal connections on the DQ/DQS signals. The DQ/DQS signal should directly connect to I/O pin instead of any other logic, If you are connecting the DQ/DQS pin to the primitive, please remove it.
  3. Based on past experience, if you have signal tap connected , it may cause you a problem . Please delete it from signal tap.

If everything is good, then perhaps, can you send me your design archive file and I can look in detail what is actually causing the error?

Let me know your feedback.

Thanks

Regards,

Aida