issue in using EMIF interface for A10 SOC evaluation board

Hello Aida,

Thank you so much for your support.

i think the emif ip which is there in the qsys and the one in example design are different. For example mem_alert_n pin is not there in the example design.

For this RevC A10 evaluation board i need to use the example design(design from rocketboards) instead of "A10 SOC development kit with DDR HILO for FPGA(x72)" which is there in qsys, as the physical routing is only for x64 and there is no provision to connect 8 ECC pins (x72)and I need to check the feasibility of connecting the extra pins like mem_alert_n in the evaluation board schematic.