issue in using EMIF interface for A10 SOC evaluation board

thanks Aida for your response.

I am using A10 Soc Evaluation board Rev C(production sample)A10AS066N3F40I2SG.

point 1: mem* and rzq* signals are exported to top level and oct_rzqin pin is connected to the ground in the schematic.

point 2: the DQ/DQS signals are directly connected to the pins.

point 3: i am not connecting signal tap

this error is coming during the Analysis & synthesis phase.

I want to add a few points, here in the example design tab in EMIF GUI i chose target development kit as "A10 SOC development kit with DDR HILO for FPGA(x72),

Since i didn't find the physical routing of dq pins to the connector for x72, and it has only 64 bit connection from FPGA to the connector,I modified the gui with the parameters in the example design which is mentioned below.

ref: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an829.pdf page: 8,

the board schematics is there in the following link

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html