Is there a standard way to store and retrieve "build information" of an FPGA design?

Hi,

Do you have any updates?

Thanks.

Hi,

You may go to Assignments > Settings > IP Generation HDL preference, set to VHDL

Thanks.

​The project is now being compiled using a script based flow. It shall generate the Qsys system before synthesis. I did include the .qsys file into the design so Quartus automatically generates the Qsys system. However, I noticed that it (automatically) generates verilog synthesis files rather than VHDL files. It is not clear how to specify Quartus to automatically generate VHDL synthesis files instead when .qsys file is included into the project.

I wrote a custom tcl script that generates a VHDL file with the compilation data and time, and the git hash values. This package is included into a register bank in the design. The register bank already exists and stores many different type of data used by the design. The register bank code is all in VHDL.

The compilation data and time, and the git hash values for the repositories that form the project can be read by using system console.

Hi,

May I know if you have any updates?

Thanks.

Hi,

You have to execute the qsys-generate in the command line terminal instead of the TCL Console in the Intel Quartus Prime software.

You may specify the language when you execute this command. Attached is the help for your reference

Thanks.

Executing the qsys-generate from tcl produces error as shown in the screenshot. Do I need to load some tcl package to make this work?

Including the .qsys into the Quartus project file seems to generate a system where everything is in verilog and it seems to clash with some other files that already exist with those names. If I include the .qsys file, how do I specify that when Quartus generates this system, it should be via VHDL files. There must be some global assignment that can be put into the .qip file.

Hi,

qsys-generate is the TCL command that is used to generate the Qsys system. The software will regenerate the system even if you did not specify the command, provided you have added the .qsys file (not .qip) in the project.

Thanks.

YY, do I understand correct that there is no command within tcl in Quartus that ​carries out Qsys generation?

Hi,

Q1: You may use the following to run the TCL script.

quartus_sh -t first.tcl

Q2: Yes. The software will regenerate the Qsys system if you add the .qsys file in the project.

Thanks.