Is there a standard way to store and retrieve "build information" of an FPGA design?

I wrote a custom tcl script that generates a VHDL file with the compilation data and time, and the git hash values. This package is included into a register bank in the design. The register bank already exists and stores many different type of data used by the design. The register bank code is all in VHDL.

The compilation data and time, and the git hash values for the repositories that form the project can be read by using system console.