Is there a standard way to store and retrieve "build information" of an FPGA design?

​The project is now being compiled using a script based flow. It shall generate the Qsys system before synthesis. I did include the .qsys file into the design so Quartus automatically generates the Qsys system. However, I noticed that it (automatically) generates verilog synthesis files rather than VHDL files. It is not clear how to specify Quartus to automatically generate VHDL synthesis files instead when .qsys file is included into the project.