Is there a standard way to store and retrieve "build information" of an FPGA design?

Executing the qsys-generate from tcl produces error as shown in the screenshot. Do I need to load some tcl package to make this work?

Including the .qsys into the Quartus project file seems to generate a system where everything is in verilog and it seems to clash with some other files that already exist with those names. If I include the .qsys file, how do I specify that when Quartus generates this system, it should be via VHDL files. There must be some global assignment that can be put into the .qip file.