I/O Pins show 1.12V on scope

Are you using a voltmeter? If yes you really need to see your signal with a scope. If it is oscillating the DC level shown by the voltmeter doesn't really mean a lot.

Some unused pins, or pins used as inputs, can be connected to the bank's VCCIO through a weak pull-up. This could be what you see. Do you know the pin's bank I/O voltage?

Hi,

So all of my bank's are set to 3.3V for VCCIO. I am using a digital o-scope to see the voltage levels. My investigation all started when I wanted to use a dedicated clock pin as an input for my clock source in a design and then generate a pll using the megafunction altpll to output a clean looking square wave. My input signal clock looks more like a sine wave... but basically what is happening is that my signal gets shifted to center at around 1.12V. So i checked out several other I/O pins that are not programmed to be used (so I"m not sure if they are put into a tri-state HI-Z or what) but I'm seeing the same type of behavior (1.12V DC signal at whatever random pin I scope as well).

So because I'm using 3.3V logic for all my I/O i assumed that the only thing close to 1.12 is the power VCCINT at 1.2. My PLL's power pins are 2.5V through ferrite beads I believe.

When you say you see a DC voltage of 1.12V, I assume that you mean you see only a DC voltage, and no switching AC signal on top of that. If so, here are some things you might consider:

1. Double-check your assignments. Have you assigned the correct signal to the correct pin, assigned it as an output, and selected the correct output standard?

2. Simulate the circuit. Does the simulator show the expected signal on that pin?

3. If the above are all OK, think about the bandwidths of your device and your oscilloscope. I recently saw a similar DC level when I inadvertently drove a 1 GHz PLL output signal to a 2.5V CMOS output. If your signal exceeds the bandwidth capability of the output pin/IO standard or the bandwidth of your scope, you could see a mid-signal DC level.

Correct, I only see the DC voltage; no AC switching.

As for the bandwidth of the o-scope I've got a 100MHz oscope and my signal is 32MHz sine wave. I'm confident bandwidth on my oscope is not an issue when detecting my clock signal. It's possible that the 1.12V DC signal that I"m seeing is actually an AC on all pins above 100MHz but I would not know where that signal could be generated from. The only other sources/signals going to my board is DC power: 3v3, 2v5 and 1v2. I guess what is throwing me off is that I see this 1.12V shift at all I/O pins.

I've scoped my clock signal when floating with my scope and I see what I'm expecting (0-3.3V swing AC signal at 32MHz). If I apply it to an op amp negative terminal input, I don't see any shift when i scope the input (positive terminal tied to ground via pull-down). When I apply it to the FPGA dedicated clock input pin or any general I/O pin just to test, I get this 1.12V shift (so AC signal looks like it's from 1.12 to 4.42).

What was really confusing for me is that I was getting this same shift even with no power to my FPGA board.

This made me think I had some grounding problems but I think my grounds are okay.. Maybe I need several grounding lines? That is... my clock is on a breadboard and has a separate power supply than the DC jack to my FPGA board. But I've tied the grounds together via one line. Maybe I need to make the grounding connection at several points of contact however?

I will have to try simulating the circuit, however I'm not really sure what kind of model I should use for an I/O pin on this FPGA. Any suggestions? I'll double check my pin assignment again but I'm pretty sure I've got this straightened out. One thing I was curious about though is the PLL output. Since the supply for the PLL is 2.5V does that mean I can not output a 3.3V LVCMOS for the PLL? What logic standard do you suggest? For the dedicated clock input, should I use 3.3V LVCMOS or a TTL standard?

Thanks!

Sounds like the bandwidth idea is not the problem.

I think I may have misunderstood you earlier. I thought earlier that you were seeing the 1.12V on an FPGA output pin. Now I see that you are observing that on an input pin. In that case, there may be nothing wrong with the FPGA, as Daixiwen suggests. Is it possible your clock circuit output is AC coupled? In that case, it will float to whatever DC level the FPGA pin naturally wants to source. Perhaps you should take a careful look at your clock circuit. It's design needs to such that if they share a common ground, as they should, then it must drive the FPGA pin to valid high and low levels for whatever logic standard you choose. That includes being able to overcome a high impedance that might be sourcing or sinking a small amount of current to some level other than ground on the FPGA input.

The simulation I was suggesting was just a simple RTL simulation of your FPGA design to increase your confidence that your pin will actually have the expected signal. (not an analog simulation) Since you are looking at an input pin, that suggestion does not have much merit anymore.

Is the FPGA configured? Do you have anything in the flash? Because if the FPGA isn't configured, then you can verify that your problem isn't related to the HDL design. An unconfigured FPGA will have all its I/O pins set in high impedance mode with weak pull-ups to VCCIO.

I assume that you checked your power supplies, and that you are delivering nice DC to VCCINT, VCCA, and VCCIO. You must supply DC to all the supplies, even if you aren't using the associated PLL or I/O bank.

Is your FPGA soldered correctly? Bad ground connection could also give those kind of weird results.

Are you sure that the pinout on your PCB is correct and that the FPGA is with the correct orientation?

Hi,

I'm sorry for not responding earlier. The FPGA is configured and so is the configuration device (EPCS16). I checked the power supplies and these do look steady and clean. I have a separate supply for the PLL I/O bank and these also look clean. I did a ring out to make sure my board headers are indeed soldered and tied to the correct FPGA I/O pins.

So I'm thinking that maybe my problem is that I am not using the dedicated clk input pins correctly to latch an external clock. It makes sense now that I'm seeing this voltage (1.12) if the pins I'm using are in high impedance state and tied to supply through weak pullup. Should I be using Altera megafunction ALTCLKCNTRL to setup an external pin, and then an additional megafunction for the PLL and then route the PLL to an output PLL pin?

That is, should I instantiate ALTCLKCNTL to use clk0 dedicated clock line to latch my external clock signal? I then want to see a 'clean' signal at a PLL output. How does one make these connections typically (do I need an instantiation of both ALTCLKCNTL and ALTPLL)

Thanks!