I/O Pins show 1.12V on scope

Hi,

I'm sorry for not responding earlier. The FPGA is configured and so is the configuration device (EPCS16). I checked the power supplies and these do look steady and clean. I have a separate supply for the PLL I/O bank and these also look clean. I did a ring out to make sure my board headers are indeed soldered and tied to the correct FPGA I/O pins.

So I'm thinking that maybe my problem is that I am not using the dedicated clk input pins correctly to latch an external clock. It makes sense now that I'm seeing this voltage (1.12) if the pins I'm using are in high impedance state and tied to supply through weak pullup. Should I be using Altera megafunction ALTCLKCNTRL to setup an external pin, and then an additional megafunction for the PLL and then route the PLL to an output PLL pin?

That is, should I instantiate ALTCLKCNTL to use clk0 dedicated clock line to latch my external clock signal? I then want to see a 'clean' signal at a PLL output. How does one make these connections typically (do I need an instantiation of both ALTCLKCNTL and ALTPLL)

Thanks!