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Altera_Forum
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11 years ago

I/O Pins show 1.12V on scope

I have a small custom board that is just a fanout of the I/O pins and PLL and dedicated Clock pins using a EP3C40 (Quad Plastic 240 pin pack) FPGA. I have scoped out several I/O and dedicated CLK pin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

So all of my bank's are set to 3.3V for VCCIO. I am using a digital o-scope to see the voltage levels. My investigation all started when I wanted to use a dedicated clock pin as an input for my clock source in a design and then generate a pll using the megafunction altpll to output a clean looking square wave. My input signal clock looks more like a sine wave... but basically what is happening is that my signal gets shifted to center at around 1.12V. So i checked out several other I/O pins that are not programmed to be used (so I"m not sure if they are put into a tri-state HI-Z or what) but I'm seeing the same type of behavior (1.12V DC signal at whatever random pin I scope as well).

So because I'm using 3.3V logic for all my I/O i assumed that the only thing close to 1.12 is the power VCCINT at 1.2. My PLL's power pins are 2.5V through ferrite beads I believe.