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Altera_Forum
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11 years ago

I/O Pins show 1.12V on scope

I have a small custom board that is just a fanout of the I/O pins and PLL and dedicated Clock pins using a EP3C40 (Quad Plastic 240 pin pack) FPGA. I have scoped out several I/O and dedicated CLK pin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Is the FPGA configured? Do you have anything in the flash? Because if the FPGA isn't configured, then you can verify that your problem isn't related to the HDL design. An unconfigured FPGA will have all its I/O pins set in high impedance mode with weak pull-ups to VCCIO.

I assume that you checked your power supplies, and that you are delivering nice DC to VCCINT, VCCA, and VCCIO. You must supply DC to all the supplies, even if you aren't using the associated PLL or I/O bank.

Is your FPGA soldered correctly? Bad ground connection could also give those kind of weird results.

Are you sure that the pinout on your PCB is correct and that the FPGA is with the correct orientation?