I/O Pins show 1.12V on scope

Correct, I only see the DC voltage; no AC switching.

As for the bandwidth of the o-scope I've got a 100MHz oscope and my signal is 32MHz sine wave. I'm confident bandwidth on my oscope is not an issue when detecting my clock signal. It's possible that the 1.12V DC signal that I"m seeing is actually an AC on all pins above 100MHz but I would not know where that signal could be generated from. The only other sources/signals going to my board is DC power: 3v3, 2v5 and 1v2. I guess what is throwing me off is that I see this 1.12V shift at all I/O pins.

I've scoped my clock signal when floating with my scope and I see what I'm expecting (0-3.3V swing AC signal at 32MHz). If I apply it to an op amp negative terminal input, I don't see any shift when i scope the input (positive terminal tied to ground via pull-down). When I apply it to the FPGA dedicated clock input pin or any general I/O pin just to test, I get this 1.12V shift (so AC signal looks like it's from 1.12 to 4.42).

What was really confusing for me is that I was getting this same shift even with no power to my FPGA board.

This made me think I had some grounding problems but I think my grounds are okay.. Maybe I need several grounding lines? That is... my clock is on a breadboard and has a separate power supply than the DC jack to my FPGA board. But I've tied the grounds together via one line. Maybe I need to make the grounding connection at several points of contact however?

I will have to try simulating the circuit, however I'm not really sure what kind of model I should use for an I/O pin on this FPGA. Any suggestions? I'll double check my pin assignment again but I'm pretty sure I've got this straightened out. One thing I was curious about though is the PLL output. Since the supply for the PLL is 2.5V does that mean I can not output a 3.3V LVCMOS for the PLL? What logic standard do you suggest? For the dedicated clock input, should I use 3.3V LVCMOS or a TTL standard?

Thanks!