I/O Pins show 1.12V on scope

Sounds like the bandwidth idea is not the problem.

I think I may have misunderstood you earlier. I thought earlier that you were seeing the 1.12V on an FPGA output pin. Now I see that you are observing that on an input pin. In that case, there may be nothing wrong with the FPGA, as Daixiwen suggests. Is it possible your clock circuit output is AC coupled? In that case, it will float to whatever DC level the FPGA pin naturally wants to source. Perhaps you should take a careful look at your clock circuit. It's design needs to such that if they share a common ground, as they should, then it must drive the FPGA pin to valid high and low levels for whatever logic standard you choose. That includes being able to overcome a high impedance that might be sourcing or sinking a small amount of current to some level other than ground on the FPGA input.

The simulation I was suggesting was just a simple RTL simulation of your FPGA design to increase your confidence that your pin will actually have the expected signal. (not an analog simulation) Since you are looking at an input pin, that suggestion does not have much merit anymore.