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New ContributorInternal LVDS loopback in Agilex I/O tile
Hi, I’m trying to figure out if it’s possible on Agilex 5 to connect an internal output buffer to the true-differential LVDS input buffer inside the same I/O tile to create an internal loopback without routing through the package pins.
The goal is to replicate the kind of setup used in this paper, where an output driver feeds a differential input (comparator) entirely inside the FPGA to build an ADC. This was done on an Xilinx Ultrascale+, while I'd like to do it on an Agilex 5. I’ve tried using the GPIO and LVDS SERDES IPs, but both seem to route only to the pads.
Is there any way in Quartus Prime Pro or with the Agilex GPIO/SERDES IPs to tie an output buffer directly to the differential input buffer internally, or is this physically impossible on Agilex 5?
Thanks!
2 Replies
Farabi_AlteraRegular Contributor
AqidAyman_AlteraHello,
If you refer to this document:
You can find that this document explains the structure of the I/O registers, consisting of three paths: input path (from input pin to core), output path (from core to output pin), and output enable path (to output buffer). It indicates that the input and output paths are designed to interface between the FPGA core fabric and the external I/O pins via these internal registers and buffers.
