HaakolivNew Contributor2 months agoInternal LVDS loopback in Agilex I/O tile Hi, I’m trying to figure out if it’s possible on Agilex 5 to connect an internal output buffer to the true-differential LVDS input buffer inside the same I/O tile to create an internal loopback witho...Show More
Recent Discussionsintel_onchip_Memory II RAM: r/w doesn t work from FPGA but from HPSSolvedPower Rating Required for RZQ Resistor on Cyclone V SEMAX 10. No 3.0 V Schmitt Trigger I/O standardArria 10: Remote Update may brick FPGA and Factory Fallback won't workUnable to program EPCQ16A on custom cyclone IV board - error during jic flashing.