Internal LVDS loopback in Agilex I/O tile

Hello,

If you refer to this document:

https://www.intel.com/content/www/us/en/docs/programmable/813934/25-1-1/buffers-and-registers-60545.html

You can find that this document explains the structure of the I/O registers, consisting of three paths: input path (from input pin to core), output path (from core to output pin), and output enable path (to output buffer). It indicates that the input and output paths are designed to interface between the FPGA core fabric and the external I/O pins via these internal registers and buffers.