Forum Discussion
Honored Contributorinterface stratixIV with an external ultrafast comparator
Hi everybody :)
we need to interface ultrafast comparator- ADCMP572 - of analog device to a stratix4 device to perform one bit conversion. we expect that the comparator will ouput very short pulses(200 ps). The goal is to sample those pulses with FPGA. The comparator datasheet is attached 1) from a physical point of view, at which FPGA INPUT should we connect the output of the comparator -CML- in order that the short pulses can travel the FPGA with a minimum distortion ? must we connect to stratixIV transceiver only or can we to another inputs ? 2) we need to drive the LATCH differential input with a minimum jitter (<100ps) ? From which output of FPGA should we drive it ? must we connect to stratixIV transceiver only or can we to another inputs ? Waiting for your response.. Shalom30 Replies
Altera_ForumOK!
What about if we use only physical i/o of transceiver(transmitter for Latch input, and Receiver for Comparator output) without using Transceiver MegaFunction, but using a custom code based on PLL's (that can achieve a 78ps resolution) ? will we able to utilize the entire performance of the i/o?- Altera_Forum
CML sounds O.K. It's important to choose an I/O standard that can work DC coupled.
Regarding driving the latch from the FPGA. I fear, only Gigabyte transceivers can provide the intended bit timing through serializer. I fear however, that the overall jitter performance won't be better than achieved by the receiver alone. But if you provide the option in your hardware design, you can operate the comparator latched or pass-through as well and test what's better. To fully utilize the jitter performance of the comparator, you would need an external timing generator, I think. - Altera_Forum
Hi FvM and JosyB
Thank's for your interess at the problem and for the Help ;) 1) purpose of latch input: in applications where the sampled signal is periodic, we can at each period, sample the input at different phase of the period with the help of the Latched input(where the Hold and Setup time is relatively low - 5/15 ps) we can have a relatively high sampling rate of the periodic signal. from a voltage point of view, is the output of the Comparator correspond to the input of Gigabit Transceiver of stratixIV ? What about the Lacth input ? From a voltage point of view - From a physical point of view - where should we connect it to the FPGA? Shalom - Altera_Forum
I also prefer to evaluate the actual device behaviour empirically and determine e.g. sampling time uncertainty. The required 100ps jitter should be achieved by Stratix IV according to the data rate specification, I think.
- Altera_Forum
The internal sampling is 'optimized' for centered aligned data in a communications channel. If the data is not properly aligned we get an error and do the error recovery.
In the case of using this mechanism for asynchronous sampling the output of the deserialiser may possibly not truthfully represent that input as we don't have any real idea how it behaves when e.g. the data changes state at the sampling moment. Of course (quite probably) it may just go fine, some deeper insight how the GT receiver operates would help here. On the other hand the latch feature in the comparator is well specified. Now shalom could connect a GT output as the latch clock in his design anyway. This way he can try both modes. Interesting exercise!? - Altera_Forum--- Quote Start --- In the other case we rely on the sampling mechanism built into the the GT receiver, which is for receiving centered aligned data. --- Quote End --- Of course. But what problems do you expect when sampling asynchronous data? I can't see any.
- Altera_Forum
Using the latch feature of the comparator would guarantee proper sampling by the GT receiver. In the other case we rely on the sampling mechanism built into the the GT receiver, which is for receiving centered aligned data. But it is certainly worth considering. Note that the comparator's data sheet specifies a 80 ps minimum pulse width or 6.25 GHz.
- Altera_Forum--- Quote Start --- I think that making use of the latch function of the comparator is the only way to make it work. --- Quote End --- Why, the input bitstream will be latched by the receiver as well. A single bit can be either '0' or '1', you don't get more information by latching it externally before. Furthermore, not latching the signal will increase the available time resolution up to the maximum bit rate of the Statix IV device. But implementation details depend of course on the exact design purpose, that hasn't been said yet.
- Altera_Forum
I think that making use of the latch function of the comparator is the only way to make it work. By connecting the latch input to a GT output generating a 5GHz clock the output timing of the comparator is now synchronous to the reference clock of the GT receiver. The GT receiver will have to be kept into the LTR mode as the data signal has no clock information embedded. I suppose phase shifting the reference input clock of the GT receiver will be useful in aligning the data input.
- Altera_Forum
1. To achieve 200 ps or better timing resolution, you absolutely need the Gigabit receivers deserializer operation. You have to operate the receiver DC coupled, in basic mode, without any automatic alignment or other special functions.
2. I don't see a purpose for latched comparator operation, as far as you described the application.
