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Altera_Forum's avatar
Altera_Forum
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16 years ago

interface stratixIV with an external ultrafast comparator

Hi everybody :) we need to interface ultrafast comparator- ADCMP572 - of analog device to a stratix4 device to perform one bit conversion. we expect that the comparator will ouput very short...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The internal sampling is 'optimized' for centered aligned data in a communications channel. If the data is not properly aligned we get an error and do the error recovery.

In the case of using this mechanism for asynchronous sampling the output of the deserialiser may possibly not truthfully represent that input as we don't have any real idea how it behaves when e.g. the data changes state at the sampling moment. Of course (quite probably) it may just go fine, some deeper insight how the GT receiver operates would help here. On the other hand the latch feature in the comparator is well specified.

Now shalom could connect a GT output as the latch clock in his design anyway. This way he can try both modes. Interesting exercise!?