interface stratixIV with an external ultrafast comparator

Hi FvM and JosyB

Thank's for your interess at the problem and for the Help ;)

1) purpose of latch input: in applications where the sampled signal is periodic, we can at each period, sample the input at different phase of the period with the help of the Latched input(where the Hold and Setup time is relatively low - 5/15 ps) we can have a relatively high sampling rate of the periodic signal.

from a voltage point of view, is the output of the Comparator correspond to the input of Gigabit Transceiver of stratixIV ?

What about the Lacth input ? From a voltage point of view - From a physical point of view - where should we connect it to the FPGA?

Shalom