interface stratixIV with an external ultrafast comparator

CML sounds O.K. It's important to choose an I/O standard that can work DC coupled.

Regarding driving the latch from the FPGA. I fear, only Gigabyte transceivers can provide the intended bit timing through serializer. I fear however, that the overall jitter performance won't be better than achieved by the receiver alone. But if you provide the option in your hardware design, you can operate the comparator latched or pass-through as well and test what's better. To fully utilize the jitter performance of the comparator, you would need an external timing generator, I think.