open01
Occasional Contributor
4 years agoInterconnect delay with Input2reg
Hi All,
I am using the CycloneV device.
I use logiclock to fix placement position in the same LAB. But when I set different input delays, routing at the same position produces different results.
This path is the path directly from the I/O pad to the first register.
As shown in fig,
Is there any way that I can limit the delay range of this IC?
Best regards.