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open01's avatar
open01
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Interconnect delay with Input2reg

Hi All, I am using the CycloneV device. I use logiclock to fix placement position in the same LAB. But when I set different input delays, routing at the same position produces different results. ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

That's kind of the point of set_input_delay. The larger value you give for -max, the more time the router has to play with, so it may add more routing between the I/O and the input register. What is your goal here and what does your .sdc look like?

  • open01's avatar
    open01
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi sstrell,

    Thank you for your help,

    I have 12 different data input from 12 I/O pads, and they will enter 12 different input first register respectively.

    I use logiclock to keep all registers close to their own I/O pads.

    But the data delay of each path has a big gap, I want to know how can I make their values closer.

    Best regards.