Interconnect delay with Input2reg

First of all, don't use Logic Lock. Rely on your set_input_delay constraints to have the registers placed close to the I/O by the Fitter. You could also use the Fast Input Register assignment to make use of the registers right in the I/O element. Second, there are some additional constraints (like set_data_skew I think) that you could use if you're trying to do matching. I'm not super familiar with using them so somebody else could chime in on that.