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Helen5's avatar
Helen5
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3 years ago
Solved

Intel FPGA Questor simulation doesn't see lower level components

Hi,
I am simulating a design which has a couple of levels using GUI. When I choose the top level to simulate, I could not see the lower level components below it, thus cannot add the signals on those lower levels to the waveform window. This used to be possible in ModelSim. I tried to set the EDA netlist writer setting "Maintain Hierarchy" as "On", but it doesn't make difference. I am using the Lite version by the way.

Here is the screenshot to show what I mean. I would like to see other components below processor1 (e.g. datapath) in the sim window, and be able to add the signals on datapath to the waveform window, but this seems impossible from the GUI.

  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)

    Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator

     

    I am not too sure why the changes though, people from the Siemen probably know this.

    A few ways to get full visibility are:

    1) Enter below command to get the full visibility. By adding -voptargs=+acc .

    vsim -voptargs=+acc work.processor1

    2) Right-click the processor1 and select simulate. Instead of double-click.

    Best Regards,

    Richard Tan

13 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Could you share the project so I can duplicate this issue on Questa and modelsim?

    Do you just invoke the simulator tool and compile/simulate the design?

    Or you are using nativelink or scripted simulation flow?


    Best Regard,

    Richard Tan


    • Helen5's avatar
      Helen5
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      3 years ago

      Hi Richard,

      Thanks for you quick reply.

      I am using NativeLink flow, without any scripts. i.e. compile under Quartus Prime, then Tools -> Run Simulation Tool -> RTL simulation

      By the way, the version I am using doesn't allow me to create a script for simulation, there is no such option under the Tools manual.

      Please see attached project file for the design.

    • Helen5's avatar
      Helen5
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      3 years ago

      Hi Richard,

      Any though on this?

      Thanks

  • RichardT_altera's avatar
    RichardT_altera
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    3 years ago

    Sorry for the late reply.

    I not sure why there is a different between Modelsim vs Questasim.

    But I found a way to see the lower level component. Highlight all the module in the work project and right-click, simulate.

    This will show up everything.

    Best Regards,

    Richard Tan

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

    • Helen5's avatar
      Helen5
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      3 years ago

      Hi Richard,

      Thanks for looking into this.

      I can see the lower level components.

      My problem with Questa Intel FPGA is that once started simulating a components, it doesn't show any components under it, thus no way to see the waveforms of the signals in these lower level components.

      Regards

      Helen

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi Helen,


    Do you got the same behaviour with Modelsim?

    Could you share the testbench or screenshot here so I can see what goes wrong?

    Correct me if I am wrong. I do not see a testbench in the design attached previously.


    Best Regards,

    Richard Tan


    ps. Please be informed that there will be delay in response in the following week due to holiday season.


    • Helen5's avatar
      Helen5
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Richard,

      No, their was no problem when ModelSim-Altera was used as the simulator.

      I don't have a testbench for this project. Here is a script is used as the macro file (.do).

      add wave -position insertpoint \
      sim:/processor1/output_data \
      sim:/processor1/inputdata
      add wave -position insertpoint \
      sim:/processor1/clk
      add wave -position insertpoint \
      sim:/processor1/reset
      add wave -position insertpoint \
      sim:/processor1/b2v_dataPathInst/b2v_Regs/registers
      add wave -position insertpoint \
      sim:/processor1/b2v_RAMInst/mem_table
      force -freeze sim:/processor1/clk 1 0, 0 {50 ps} -r 100
      force -freeze sim:/processor1/reset 1 0
      force -freeze sim:/processor1/reset 0 300
      force -freeze sim:/processor1/inputdata 10#99 0

      As Qsim cannot see the lower level components, so the commands such as sim:/processor1/b2v_dataPathInst/b2v_Regs/registers will cause an error message.

      Basically to simulate the project, a clock and high active reset are needed, inputdata is not essential.

      Regards

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Wishing you a Happy New Year 2023!

    My apology for the late reply as I was on vacation last week.

    I seem to be able to simulate the same result using both Questa and Modelsim.

    Attached the simulation screenshot between Questa (left) and Modelsim(right). Using the cmd: do testprocessor.do @ ../studentProcessor/simulation/modelsim

    I don't quite get what's wrong here. Do you mind to pinpoint the expected behavior vs the current behavior?

    Best Regards,

    Richard Tan

    • Helen5's avatar
      Helen5
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Richard,

      Thanks for taking timing looking into this.

      This is the screenshot before I click processor1 to simulate it.

      this is the screenshot I have after clicking processor1,

      As you can see, I cannot see the hierarchy below processor1.

      Is it because I am using a lite version of Quartus?

      Regards

      Helen

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)

    Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator

     

    I am not too sure why the changes though, people from the Siemen probably know this.

    A few ways to get full visibility are:

    1) Enter below command to get the full visibility. By adding -voptargs=+acc .

    vsim -voptargs=+acc work.processor1

    2) Right-click the processor1 and select simulate. Instead of double-click.

    Best Regards,

    Richard Tan

    • Helen5's avatar
      Helen5
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Richard,

      Yes, it worked. Thank you so much for your help.

      Regards

      Helen

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Thank you for acknowledge the solution provided.

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you.


    Best Regards,

    Richard Tan