Forum Discussion

New Contributor

3 years ago

Solved

Intel FPGA Questor simulation doesn't see lower level components

Hi, I am simulating a design which has a couple of levels using GUI. When I choose the top level to simulate, I could not see the lower level components below it, thus cannot add the signals on tho...

RichardT_altera
3 years ago
Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)

Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator

I am not too sure why the changes though, people from the Siemen probably know this.

A few ways to get full visibility are:

1) Enter below command to get the full visibility. By adding -voptargs=+acc .

vsim -voptargs=+acc work.processor1

2) Right-click the processor1 and select simulate. Instead of double-click.

Best Regards,

Richard Tan

RichardT_altera

Super Contributor

3 years ago

Wishing you a Happy New Year 2023!

My apology for the late reply as I was on vacation last week.

I seem to be able to simulate the same result using both Questa and Modelsim.

Attached the simulation screenshot between Questa (left) and Modelsim(right). Using the cmd: do testprocessor.do @ ../studentProcessor/simulation/modelsim