Forum Discussion
New ContributorIntel FPGA Questor simulation doesn't see lower level components
Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)
Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator
I am not too sure why the changes though, people from the Siemen probably know this.
A few ways to get full visibility are:
1) Enter below command to get the full visibility. By adding -voptargs=+acc .
vsim -voptargs=+acc work.processor1
2) Right-click the processor1 and select simulate. Instead of double-click.
Best Regards,
Richard Tan
Super ContributorSorry for the late reply.
I not sure why there is a different between Modelsim vs Questasim.
But I found a way to see the lower level component. Highlight all the module in the work project and right-click, simulate.
This will show up everything.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorHi Richard,
Thanks for looking into this.
I can see the lower level components.
My problem with Questa Intel FPGA is that once started simulating a components, it doesn't show any components under it, thus no way to see the waveforms of the signals in these lower level components.
Regards
Helen
