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Helen5's avatar
Helen5
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Intel FPGA Questor simulation doesn't see lower level components

Hi, I am simulating a design which has a couple of levels using GUI. When I choose the top level to simulate, I could not see the lower level components below it, thus cannot add the signals on tho...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)

    Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator

     

    I am not too sure why the changes though, people from the Siemen probably know this.

    A few ways to get full visibility are:

    1) Enter below command to get the full visibility. By adding -voptargs=+acc .

    vsim -voptargs=+acc work.processor1

    2) Right-click the processor1 and select simulate. Instead of double-click.

    Best Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Helen,


Do you got the same behaviour with Modelsim?

Could you share the testbench or screenshot here so I can see what goes wrong?

Correct me if I am wrong. I do not see a testbench in the design attached previously.


Best Regards,

Richard Tan


ps. Please be informed that there will be delay in response in the following week due to holiday season.


Helen5's avatar
Helen5
Icon for New Contributor rankNew Contributor
3 years ago

Hi Richard,

No, their was no problem when ModelSim-Altera was used as the simulator.

I don't have a testbench for this project. Here is a script is used as the macro file (.do).

add wave -position insertpoint \
sim:/processor1/output_data \
sim:/processor1/inputdata
add wave -position insertpoint \
sim:/processor1/clk
add wave -position insertpoint \
sim:/processor1/reset
add wave -position insertpoint \
sim:/processor1/b2v_dataPathInst/b2v_Regs/registers
add wave -position insertpoint \
sim:/processor1/b2v_RAMInst/mem_table
force -freeze sim:/processor1/clk 1 0, 0 {50 ps} -r 100
force -freeze sim:/processor1/reset 1 0
force -freeze sim:/processor1/reset 0 300
force -freeze sim:/processor1/inputdata 10#99 0

As Qsim cannot see the lower level components, so the commands such as sim:/processor1/b2v_dataPathInst/b2v_Regs/registers will cause an error message.

Basically to simulate the project, a clock and high active reset are needed, inputdata is not essential.

Regards