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Helen5's avatar
Helen5
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3 years ago
Solved

Intel FPGA Questor simulation doesn't see lower level components

Hi, I am simulating a design which has a couple of levels using GUI. When I choose the top level to simulate, I could not see the lower level components below it, thus cannot add the signals on tho...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Ah! I think there is a slight different between Questa and Modelsim. The double-click on the processor1 in Modelsim provide full visibility into every aspect of the design (+acc=<full>). While Questa only provide visibility to ports only. (+acc=p)

    Reference on -voptargs: https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator

     

    I am not too sure why the changes though, people from the Siemen probably know this.

    A few ways to get full visibility are:

    1) Enter below command to get the full visibility. By adding -voptargs=+acc .

    vsim -voptargs=+acc work.processor1

    2) Right-click the processor1 and select simulate. Instead of double-click.

    Best Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Could you share the project so I can duplicate this issue on Questa and modelsim?

Do you just invoke the simulator tool and compile/simulate the design?

Or you are using nativelink or scripted simulation flow?


Best Regard,

Richard Tan


Helen5's avatar
Helen5
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3 years ago

Hi Richard,

Any though on this?

Thanks