Instantiate System Verilog into a VHDL Testbench

Question

Good Evening,

I am currently working on a project for school where we taking the original concepts we learned in VHDL and applying them to build the same components with System Verilog. I already have a testbench in VHDL and was wondering if there was a way to instantiate the System Verilog code to be able to utilize the already existing testbench or would it be easier to just rewrite the testbench in System Verilog?

Thank you,

-Joe

altera_forum · Answer

The answer depends on your simulator features; Modelsim-ASE is a single-language simulator, so it can only simulate VHDL or SystemVerilog, not both at the same time. Modelsim-SE is a mixed-language simulator.

If you are using Modelsim-SE, then I would recommend re-using your testbench until your SystemVerilog device-under-test works. I would then recommend re-coding the testbench using SystemVerilog, so that you get an idea how to code a SystemVerilog testbench.

Cheers,

Dave

altera_forum · Answer

To instantiate SV in VHDL, you need to declare a component in the VHDL that matches the SV module, so that the module can be maped to your VHDL Component.

altera_forum · Answer

--- Quote Start ---

To instantiate SV in VHDL, you need to declare a component in the VHDL that matches the SV module, so that the module can be maped to your VHDL Component.

--- Quote End ---

Aw, Tricky, you just spoiled several hours of frustration for Joe ...

(i.e., good recommendation)

Cheers,

Dave

altera_forum · Answer

--- Quote Start ---

Aw, Tricky, you just spoiled several hours of frustration for Joe ...

(i.e., good recommendation)

Cheers,

Dave

--- Quote End ---

The problem is, how this works is never really explained anywhere.

altera_forum · Answer

--- Quote Start ---

The answer depends on your simulator features; Modelsim-ASE is a single-language simulator, so it can only simulate VHDL or SystemVerilog, not both at the same time.

--- Quote End ---

Dave,

this link seems to indicate that modelsim- altera starter edition is mixed-language ...? (https://www.altera.com/products/design-software/model---simulation/modelsim-altera-software.html) :

starting with quartus software v15.0, the modelsim-altera edition software supports dual-language simulation. this includes designs that are written in a combination of verilog, system verilog, and vhdl languages, also known as mixed hdl.

Regards,

Josy

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Instantiate System Verilog into a VHDL Testbench

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