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Altera_Forum's avatar
Altera_Forum
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10 years ago

Instantiate System Verilog into a VHDL Testbench

Good Evening, I am currently working on a project for school where we taking the original concepts we learned in VHDL and applying them to build the same components with System Verilog. I alrea...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The answer depends on your simulator features; Modelsim-ASE is a single-language simulator, so it can only simulate VHDL or SystemVerilog, not both at the same time. Modelsim-SE is a mixed-language simulator.

If you are using Modelsim-SE, then I would recommend re-using your testbench until your SystemVerilog device-under-test works. I would then recommend re-coding the testbench using SystemVerilog, so that you get an idea how to code a SystemVerilog testbench.

Cheers,

Dave