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Honored Contributor
Honored ContributorInstantiate System Verilog into a VHDL Testbench
Good Evening, I am currently working on a project for school where we taking the original concepts we learned in VHDL and applying them to build the same components with System Verilog. I alrea...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- To instantiate SV in VHDL, you need to declare a component in the VHDL that matches the SV module, so that the module can be maped to your VHDL Component. --- Quote End --- Aw, Tricky, you just spoiled several hours of frustration for Joe ... (i.e., good recommendation) Cheers, Dave
