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Altera_Forum
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10 years ago

Instantiate System Verilog into a VHDL Testbench

Good Evening, I am currently working on a project for school where we taking the original concepts we learned in VHDL and applying them to build the same components with System Verilog. I alrea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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To instantiate SV in VHDL, you need to declare a component in the VHDL that matches the SV module, so that the module can be maped to your VHDL Component.

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Aw, Tricky, you just spoiled several hours of frustration for Joe ...

(i.e., good recommendation)

Cheers,

Dave